Millimeter-wave main memory-to-processor data bus

The mainstreaming of chip multiprocessor (CMP) architectures exact a profound impact on valuable resources, for example, L3 cache capacity, off-chip bandwidth and on-board main memory capacity. Even with latency-hiding software strategies, in a memory-starved system, a processor can remain idle for several decades of clock cycles and performance will degrade [1]. Two hardware solutions are being developed for opening the memory bottleneck; (1) Stack bare SRAM die memory, with multiplexer-demultiplexer, using through-silicon vias and place the SRAM stacks around the multi-core processor at the multi-chip carrier level [2] to increase L3 capacity and, in addition, also stack dynamic random access memory (DRAM) dies on board to increase main memory capacity needed for numerically intensive and storage intensive computations.