Synchronous parallel controller synthesis from behavioural multiple-process VHDL description

A unified framework and associated algorithms for a behavioural synthesis of parallel controllers from a multiple-process VHDL specification is presented. An extension to FSMs, based on Petri nets, is used as an internal representation of an concurrent system during the synthesis. The VHDL simulation cycle implications are explicitly implemented into the Petri net model. This model is next decomposed into a set of well formed subcontrollers and state assignments are generated.