Total Performance of 32-nm-Node Ultralow-$k$ /Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica $(k = \hbox{2.1})$

The total performance of low-
$k$
/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO,
$k = \hbox{2.1}$
) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK,
$k = \hbox{2.65}$
). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node.