The design and implementation of arbiters for Network-on-chips

Round robin arbiter and matrix arbiter mechanism are widely used in Network-on-chips. These two mechanisms are implemented in this paper. The performances in 2D-mesh topology are tested in a FPGA platform. The resource consumption and throughput between Round-robin arbiter and Matrix-arbiter are compared. Through the experiment result, we found that the Matrix-arbiter has higher throughput than the Round-robin arbiter. However the Round-robin arbiter can save much more resources than Matrix arbiter. Thus a tradeoff between the two mechanisms should be considered when design networks-on-chip arbiters.