System verifacation based on VMM and SOPC

This paper presents a new type of a more complete system verification method, which combines a high-level verification methodology based on verification methodology manual (VMM) techniques for functional simulation and system-on-a-programmable-chip (SOPC) techniques for board-level verification, effectively improve the adequacy and reliability of verification and validation efficiency. This paper gives a scalable hierarchical verification platform used systemverilog, which achieved the constraint-random stimulus generation, assertion monitoring, automatic real-time comparison for outputs and coverage statistics. Additionally, this paper describes the development of the test environment and the entire physical verification platform.