A 100MHz Digital Down Converter with modified FIR filter for wideband software-defined radios

Digital Down Converter is one of the key technologies in Software Defined Radio. In Digital Down Converter how to realize a high-speed, high-order FIR filter is an interesting problem. This paper proposes a modified Distributed Arithmetic, in which speed is improved and memory is saved compared with the traditional Distributed Arithmetic. The presented FIR filter based on the modified Distributed Arithmetic has been implemented in the form of ASIC which was fabricated in a SMIC 0.13 μm CMOS process. The chip's sample rate can reach 10MSPS in the 80MHz system clock.