MLC PRAM with SLC write-speed and robust read scheme

We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.