8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

We report low V
_t
(V
_t,Lg=1μm
=±0.26V) high performance CMOS devices with ultra-scaled T
_inv
down to T
_inv
~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T
_inv
(2) 220mV lower long channel pMOS V
_t
(3) 21%/12% pMOS/nMOS drive current increase at I
_off
=100nA/μm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T
_inv
of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.