A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.