Novel circuit design and process technology for leading-edge products

Achieving power, performance, yield and cost scaling targets at leading edge technology nodes has become significantly more challenging. Success is driven by making the optimal combination of process, design, and package decisions. In this paper, we report novel circuit design and process technologies for leading-edge products. We focus on two topics: (1) chip design optimization using extremely regular layout methodology, and (2) SiP (System in Package) with CoC (chip on chip) for 40nm technology node products.