Great reduction of interfacial traps in Al2O3/GaAs (100) starting with Ga-rich surface and through systematic thermal annealing

The quest for technologies beyond the 15 nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on alternative channel materials such as Ge and III-V compound semiconductors with inherently higher carrier mobility than those of Si. Intensive effort has been made on GaAs nMOS devices owing to GaAs's superior electron mobility and its lattice parameter close to that of Ge. Dielectric/GaAs (100) interfaces, in general, have very high interfacial trap density (D
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) at the mid-gap energy, resulting in serious Fermi-level pinning issues, and thus preventing the proper inversion response required for the inversion-channel GaAs MOS devices. To solve this problem, a number of approaches for passivating GaAs have been reported in the past decades, with one report showing good drain current in an inversion-channel GaAs MOSFET. Evaluation of D
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was usually obtained using capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics measured at room temperatures. However, due to the larger energy band-gap of GaAs as compared to that of Si, interfacial traps near the mid-gap of the dielectric/GaAs interfaces may be too slow to respond to the usual C-V and G-V characterization frequencies at room temperatures and only a small region of the whole GaAs band-gap away from the mid-gap can be measured. In this work, this inadequacy is remedied by performing additional C-V and G-V measurements at a high temperature of 150°C to probe D
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spectrums near the critical mid-gap region. Furthermore, the influence on the D
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around the mid-gap region of the dielectric/GaAs interfaces by the GaAs surface reconstructions and systematic annealing conditions has been studied.