Easily testable data path allocation using input/output registers

Most existing behavioral synthesis systems concentrate on area and performance optimization, while ignoring other design qualities such as testability. In this paper/sup /spl Dagger//, we present three algorithms for register, module, and interconnection allocation of behavioral synthesis respectively to improve testability in data path allocation without assuming any specific test strategy. By using primary input/output registers effectively, the proposed algorithms produce RTL designs with better testability, while incur low or even no hardware overhead. Four benchmarks are synthesized using the proposed approaches and the results are compared with the best results of similar works in the literature. It shows that our approaches give both higher fault coverage and lower hardware overhead.