IDD scan test method for fault localization technique on CMOS VLSI failure analysis

One of the fashionable stress test that has been practiced in CMOS VLSI recently is known as I
_DDQ
scan test. It has competency to be exercised as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. Form the results obtained during the experiment, it shows that the I
_DD
scan test can be applied effectively in triggering significant emission spot during anomalous logic transition.