Analysis of thermally enhanced SOIC packages

The thermal performance of a number of thermally enhanced small outline integrated circuit (SOIC) package designs is evaluated by means of a thermal model utilizing finite element analysis (FEA) and compared to that of a standard design. A number of enhancements are explored: reduced pad-inner lead tip spacing, fused leads, padless chip-on-lead (COL) construction, and heat slugs. In most of these cases the impact of replacing the standard epoxy molding compound (MC) with a thermally enhanced molding compound was investigated. A mathematical technique is demonstrated whereby the die (junction) temperature can be calculated at an arbitrary number of power levels and values of air velocity using the results of a small number of FEA solutions. This technique is particularly efficient when dealing with nonlinear boundary conditions involving buoyancy-driven convection and radiation. The predictions of the model were verified for one package type and shown to be in good agreement with experiment. Postprocessing of the FEA solution was performed for each design to calculate the thermal resistance of the principal heat flow paths and the partitioning of the heat dissipated by the IC among these paths. It is shown that the primary heat flow path is die-to-lead-to-circuit board-to-air and that a low junction-to-lead thermal resistance is the primary indicator of high thermal performance. The heat slug package and the COL package (when all leads have direct contact to the die) were shown to have the lowest junction-to-lead thermal resistance and best thermal performance. The use of an enhanced molding compound was shown to have a significant effect on the thermal performance only when the heat flowing from the junction to the leads flows through the molding compound. As such, it did not benefit the heat slug and optimal COL designs.