Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

This paper presents a technique called supply boosting for designing sub-1V analog/mixed-signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes containing MOSFET transistors with threshold voltages comparable to the supply voltage. SBT is based on the idea that if current consumption of the circuit block is very low, in the order of nanoamper, supply voltage could be boosted locally to higher levels during a period that the processing of input signals is done. This technique is very suitable for very-low power clocked and continuous time circuits such as level shifters, operational amplifiers, and comparators. Design of a 10-bit supply boosted (SB) SAR ADC is presented as an example of the technique. SB-SAR ADC simulated using 0.5μm CMOS process that has high-V
_T
NMOS and PMOS devices. Simulations show that the SB-SAR ADC achieves 0.24pJ/conv-step figure of merit (FOM) when operating ADC at 10KS/sec and 1.2V supply.