PCH Power gating domains implementation and design challenges

This paper discusses the methodology used for improving power savings on a new Platform Control Hub (PCH); an advanced System-on-a-Chip (SOC). Low power design techniques had evolved from those used in multiple chips on a package designs towards more efficient ones in a System-on-a-Chip (SOC). The example that this paper is based on, had improved power savings up to 47% compared to the previous generation of PCH. Thus, with the new improvement, we will see a much better battery life span for a mobile computing platform and also make desktop computing platforms more eco friendly. We will be looking at a multiple power domains design; governed by different stages of PFET switches, local power gating controller and central power gating controller implemented in the new Platform Control Hub (PCH). Further more, a newly introduced routing scheme of self-isolated repeater cells which feeds through different power domain will also be discusses; as we also look at design approaches that were taken to avoid causing a big impact to voltage drop and electro migration on power grids of different metal layers. These design are in place to further improve the standby power saving and reduce sub-threshold leakage. However, the design also introduces some challenges and trade-off between wake-up overhead and leakage savings that need to be carefully balance while conducting power delivery modeling analysis. To round up the paper, we will present measurements of power savings in gating and ungating from silicon debugs; to validate the correlation between simulation modeling and actual silicon implementation.