A 200V Partial SOI 0.18µm CMOS technology

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and area-efficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.