Application of low power technologies on video codec VLSI designs

We apply several low power technologies to save both total energy and peak power consumption for video codec VLSI designs. Our technologies include two-layer clock gating, utilization of skip mode, memory hierarchy with memory access units, and internal memory partitioning. We implement a standby mode to reduce both clock power and memory power for saving total energy. We also use a novel technology, called active period rescheduling, to reduce the peak power consumption. Applying these technologies to an H.264/AVC codec, we can achieve 43% and 45% savings in total energy for the encoder and decoder, respectively. Moreover, by applying the peak power reduction technology to the H.264/AVC decoder, we achieve 45% saving.