A novel mutli-cores MCU architecture based on data flow computing

The concept of data flow computing is increasingly being used to the multi-core and parallel computing architecture in nowadays. This paper presents a new multi-cores MCU architecture, named DFF (Data Flow driven on Function-level), which possesses the characteristics of function-level parallelism and data driven. It efficiently synthesizes the middle grain parallelism of data flow computing and the sequential computing commonly used in von Neumann structure. The main process of the design is explained by an example of data-driven computation implementing where the custom function stored in the single core (NIOSII), in the initialization phase, will begin to run only when all its operands are available, and the system will be in the sleep state when no effective data can be used to drive and the power will be saved significantly. Moreover, the multi-cores can carry out parallel operation under the data-independent. Some feasible verifications of multi-cores MCU architecture are implemented in Altera EP20K200EFC484-2 to prove the validity of this approach. It is shown that the novel architecture with DFF mode can reduces the hardware overhead and the power consumption.