Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)

A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices.