A clock network of distributed ADPLLs using an asymmetric comparison strategy

In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.