Fault collapsing with linear complexity in digital circuits

The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is proposed to reduce the size of collapsed fault sets. Experimental data show that the fault collapsing by the proposed method is more efficient than other strucural fault collapsing methods with comparative time cost are.