Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process

The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19 V in planar devices. Here the structure performance is advanced by optimizing a Very-Thin-RESURF (VTR) region (VTR Xj=0.3 /spl mu/m). This work presents a planar VTR drain extended IGFET with best case BV=25 V and R/sub sp/=0.34 m/spl Omega//spl middot/cm/sup 2/@V/sub gs/=10 V using a compressed BiCMOS VLSI, 1 /spl mu/m technology. Structure variation and thermal performance are characterized.