Novel fault localization approach for ATPG / scan-fault failures in complex sub-nano FPGA/ASIC debugging

Fault isolation in automated test pattern generation (ATPG) / scan-fault has been increasingly challenging in today's advanced integrated circuit (IC) as diagnosis results usually point to extensive faulty nets which can be physically widespread on the die. This work highlights a novel approach in understanding electrical fault data with promising physical failure analysis (PFA) results in FPGA/ASIC debugging.