Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a high-voltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to assess the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single- and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain V
_ds
and gate V
_gs
stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4V
_ds
<; V
_gs
<; 0.5V
_ds
for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.