VLSI architecture of a scalable matrix transposer

In this paper, we present an ASIC implementation of matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8/spl times/8 matrix cannot be directly obtained from a 4/spl times/4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.