A general approach in system design integrating reconfigurable accelerators

This paper introduces a fundamentally new machine paradigm, which takes into account that hardware has become soft. Along with a compilation technique, this paper introduces its implementation and application by illustrating the rDPA (reconfigurable data path array), an integrated circuit having been designed at Kaiserslautern and submitted for fabrication. This is the first implementation of a field-programmable data path array (FPDPA), which uses configurable ALU blocks (CABs) instead of CLBs (configurable logic blocks). This novel platform, provides highly efficient means of instruction level parallelism: for many applications by orders of magnitude more efficient than the traditional parallelism used in all scenes of high performance computing.