A table-based bias and temperature-dependent small-signal and noise equivalent circuit model

A new algorithm is presented for construction of accurate table-based bias and temperature dependent field-effect transistor (FET) small-signal and noise models. The algorithm performs two-dimensional (2-D) linear interpolation on a single stored data table to quickly produce bias and temperature-dependent model simulations. Comparisons of simulated FET S-parameters, noise figure, and device figures of merit (e.g., G/sub max/) versus measured data show the model to be accurate over a wide range of bias and temperatures. Model enabled simulations of a single-stage FET-based low-noise monolithic microwave integrated circuit (MMIC) amplifier are also shown to compare favorably with measured amplifier data. The new algorithm improves on previously available approaches in three ways: (1) it allows efficient and accurate small signal device and circuit simulations over bias and temperature; (2) it allows circuit optimization with respect to bias and temperature; and (3) it provides substantial data storage reduction over alternate approaches. Because one compact data table represents a single sample device, the approach can be readily adapted for use in a statistical FET model data base.