Reducing power dissipation in low voltage flash memories

A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a selected bitcell in a NOR block, the power dissipated is dominated by a band-to-band transient current. SPICE simulations show that this power can be reduced by decreasing the charge pump's slew rate and the erase threshold voltage. In an unselected bitcell, the power dissipated is the sum of band-to-band and drain charging currents. Simulations show that this power can be reduced by increasing the positive word line bias applied to unselected bitcells in the NOR block.