Differential PSK detector ASIC design for direct sequence spread spectrum radio

In this paper we present an optimized architecture for differential PSK detection which effectively minimizes the required logic complexity for ASIC implementation. This complexity reduction is obtained by carrying out intelligent truncation of the detector input words and by utilizing a bit-serial/word-parallel structure. We also show that this can be done without degrading the performance in terms of bit error rate. The structure has been implemented in a direct sequence spread spectrum transceiver circuit, and preliminary measurement results are presented.