Parallel processing clock synchronization-dispersion equalization combining loop in 112Gb/s optical coherent receivers

In optical coherent receivers, the timing error detector in synchronization loop can't detect timing errors properly from signals distorted by large dispersion and the signal processing rate in the loop is very difficult to reach required 56GHz in the 112 Gb/s PM-(D)QPSK system because of the limit of current electronic circuits. This paper proposes a novel parallel processing VCO clock synchronization loop in combination with dispersion equalization, which fulfills synchronization, equalization and polarization de-multiplexing simultaneously under the control of single VCO. Simulink simulation demonstrates the satisfied performance of the proposed parallel processing loop with 42 GHz sampling frequency and 466.67MHz digital signal processing rate.