Projected bandwidth loop - an alternative to adaptive bandwidth loops with reduced complexity

For a carrier phase positioning receiver, phase lock loop (PLL) performance is of critical importance due to the fact that the carrier phase measurements, used for determining the final positioning solution, originate from the PLL. The performance of the PLL dictates the quality of these measurements and eventually, that of the positioning solution. Total phase jitter has been identified as the metric of a PLL's performance and needs to be reduced to improve the quality of these measurements. Use of an adaptive bandwidth (B_La) architecture is a widely accepted approach to reduce this jitter, but is associated with increased processing complexity. This paper proposes the novel concept of the Projected Bandwidth (B_Lp) architecture which offers similar advantages but with reduced complexity. However, this is achieved at the cost of slight degradations in jitter reductions compared to a B_La architecture. It is shown using theoretical analysis that the use of a B_Lp architecture does not degrade the improvements by more than 3.7% of those offered by a B_La architecture. It is also shown that for Carrier-to-Noise- and Interference-Ratio (CNIR) more than 40dB-Hz, the B_Lp architecture offers the same amount of jitter reduction as a B_La architecture. This paper also discusses implementation issues and presents simulation results. It is shown that by using B_Lp, total phase jitter reduction of more than 25% can be achieved.