An 8-bit 2.5GS/s D/A converter in 0.35µ CMOS technology with improved pipeline structure

An improved pipeline structure is proposed to enhance the throughput rate of D/A converters preserving desired dynamic specifications up to near-nyquist input update rates. Utmost 100% improvement could be realized in update rate through definite number of pipeline stages in compare with the conventional pipeline methods. An 8-bit 2.5GS/s dual-channel DAC is implemented in 0.35μm CMOS technology based on the proposed improved pipeline strategy which is implemented in active area of about 0.56mm
²
and total power consumption of 110mW at 2.5GS/s throughput rate for near-nyquist input frequencies. Post-layout simulations confirm the SNDR of 48.93dB and SFDR of 63.3dB at 2.5GS/s throughput rate for lower input frequencies near 12.2MHz. The measured values are degraded to 43.9dB and 54dB for near-nyquist frequencies of output sinusoidal waveform, respectively. A novel swing reducing method for diluting clock feed through effect, a new isolation technique for eliminating the transparency of master-slave dynamic buffers and a novel method for alternate sampling between parallel channels are also presented in this paper.