Novel circuit technique for reduction of active drain current in series/parallel PMOS transistors stack

Stacking of MOS transistors [1] is used for minimization of standby current in Nano-scale CMOS circuits. Stacking of PMOS is preferred over NMOS because value of active drain current in PMOS is less than NMOS. It results because of mobility of holes in PMOS is less than mobility of electrons in NMOS [2]. In this paper we observed active drain current consumption by series/parallel combination of two and three PMOS transistors. This observation leads to propose the novel technique for reduction of active drain current in series/parallel PMOS assembly. The effect of V
GS
, V
DS
, V
SB
and intermediates node voltages is also addressed. The proposed circuit is simulated for TSMC 0.18 µm technology using Spice© simulator