Noise determination of a current conveyor in an inverting voltage amplifier configuration

Analysis concentrated on noise performance issues of a CMOS high gain second generation current conveyor (CCII∞) is presented using both simulations and measurements results. The circuit has been fabricated in a 0.35 μm CMOS process by Austria Mikro Systeme (AMS) and it is examined analytically in terms of the noise contribution of each transistor in an inverting voltage amplifier configuration. Preliminary results about the noise minimization procedure are extracted. Regarding the topology performance characteristics, the power consumption is 93 μW and the total input referred rms noise is equal to 7.03 μV for a bandwidth of 1 Hz to 100 kHz.