Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design

Through-silicon-via (TSV) becomes an emerging interconnection technology with various TSV structures, among which the annular-TSV demonstrates great application potentials because of its simple manufacturing processes and low cost. Due to the mismatch of coefficient of thermal expansion (CTE) among various materials leading to various quality and reliability issues, it is necessary to develop a novel modeling/simulation approach to help with optimizing annular-TSV structures and process parameters because the plated-Cu uniformity highly depends on Cu-plating solution, plating process and via location. Therefore, a novel sequential electro-chemical and thermo-mechanical simulation methodology was developed with simulation procedures as the electro-chemical analyses to simulate Cu-plating process, followed by the thermo-mechanical analyses (from wafer-level model, chip-level model to via-level model) to simulate key TSV insulation/plating processes using global-local and death-birth simulation methods. Based on the novel simulation methodology, this work studied the variations of plated-Cu thickness and found the stress of annular-TSVs near wafer edge was larger than that at wafer center by 16%~18% due to the Cu-plating non-uniformity. The stress of annular-TSVs would increase by 10%~31% and by 9%~27% if reducing the Cu seed thickness from 2um to 0.5um and reducing the via pitch from 300um to 150um, respectively.