Voltage scaling limitations and challenges of memory-rich nanoscale CMOS LSIs

The minimum operating voltage, V
_min
, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate V
_min
. It shows that V
_min
is very sensitive to the threshold-voltage variations, ΔV
_t
, which become more significant with device scaling, and to the lowest necessary threshold voltage, V
_t0
, of MOSFETs. As a result of comparing the V
_min
s of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest V
_min
despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To further reduce the V
_min
s of the blocks, ΔV
_t
-immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and low-V
_t0
circuits are discussed, showing the below 0.5-V era feasible to come.