Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff=100 nA/μm with VDD=1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS −0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive are thus offered with 0.94nm EOT. Mechanisms and guidelines for solving theses issues are provided after a comprehensive study here. These concepts are beneficial to either gate-first or gate-last approach with EOT scaling.