New statistical model to decode the reliability and weibull slope of high-κ and interfacial layer in a dual layer dielectric stack

Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using suitable statistical models. Direct extension of the simple statistical model used for SiON to the HK is complicated by the presence of the interfacial sub-oxide layer (IL, SiO
_x
) which is sandwiched between the HK and Si substrate. Given the dual-layer HK-IL dielectric stack, it is necessary to develop new statistical models and electrical test algorithms that can enable us to decode the reliability and Weibull slope of the individual HK and IL layers so that the relative reliability of these two layers can be studied to identify the layer which serves as a “savior” in prolonging the front end reliability of current HK based logic devices. In this study, we propose a new cumulative damage statistical model in conjunction with a two step voltage stress electrical test algorithm for sequential HK-IL breakdown which enables us to analyze the TDDB reliability of HK and IL separately.