TLU Prevention in PowerRail ESD Clamp Circuits

introduces several TLU issues in power-rail ESD clamp circuits fabricated in both low-voltage (LV) and high-voltage (HV) 40-V COMS processes. In LV CMOS process, although the TLU-free ESD-clamp circuit can be easily designed by placing double guard rings to surround each MOS devices, a specific ?>TLU-like?> failure would still occur due to the latch-on state of ESD-clamping NMOS under the system-level ESD test. In HV CMOS process, the bottleneck is that the latchup holding voltage is generally much smaller than the HV nominal operating voltage, thus inevitably leading to TLU risks in HV power-rail ESD clamp circuits. In addition to the clarification of TLU-related issues in the power-rail ESD clamp circuits, the investigation and design of TLU-free power-rail ESD clamp circuits are also introduced. These TLU-free power-rail ESD clamp circuits can guarantee robust ESD immunity without suffering TLU or any TLU-like danger in both LV and HV CMOS ICs.