TLU Dependency on PowerPin Damping Frequency and Damping Factor in CMOS Integrated Circuits1 2007 IEEE. 4.14.3 and part of 4.4 reprinted, with permission, from ShengFu Hsu and MingDou Ker, Transientinduced latchup dependence on powerpin damping frequency and damping factor in CMOS integrated circuits (abstractsection IV and figures 2, 3, 711, and 1416), in IEEE Transactions on Electron Devices, Vol. 54, no. 8, pp. 20022010, Aug. 2007. IEEE, Piscataway, NJ.

characterizes the TLU dependencies on two dominant parameters of TLU-triggering transient noises, power-pin damping frequency and damping factor. In real situations, they are strongly dependent on the system shielding, board-level noise filter, chip-/board- level layout, etc. Their impacts on the TLU immunity can be well explained in time domain by device simulation. Based on the comprehensive simulation results and experimental verifications, the board-level noise filters can be properly developed to efficiently eliminate the ESD-coupled noises for TLU prevention.