Physical Mechanism of TLU under the SystemLevel ESD Test

focuses on the clarification of TLU physical mechanism in CMOS ICs under the system-level ESD test. An underdamped sinusoidal voltage stimulus is clarified as the realistic TLU-triggering stimulus under the system-level ESD test. With the TLU characterization by device simulation and experimental verification in time domain, the specific ?>sweep-back?> current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is qualitatively proved to be the major cause of TLU. A simple 1-D analytical model of such ?>sweep-back?> current is also introduced. This model can qualitatively describe the sweep-back current dependency on the TLU-triggering stimulus under the system-level ESD test.