A CRT-Based BCH Encoding and FPGA Implementation

Additional coding gain of about 0.6 dB is observed for binary BCH codes compared to RS codes with similar code rate and codeword length under AWGN channel. This paper presents a new CRT-based (Chinese Remainder Theorem) BCH encoding. CRT-based encoding method has higher speed than original LFSR encoding method. An encoding scheme is proposed which makes trade-off between resource usage and speed possible. In the second part of this paper, high speed FPGA implementation of this new type BCH encoder is given. Large fan-out of some XOR gate in LFSR was greatly reduced using CRT-based encoder. Several new implementation steps are proposed for real implementation. To reduce resource usage, Novel pipelined polynomial multiplier architecture is used. Common Subexpression Elimination (CSE) is used for optimization. The experiment result showed 23% reduction in XOR gate and 13% reduction in register. The maximum frequency is 358 MHz when implemented using Device XC2VP30 of Vertex II PRO Family.