Co-design considerations for frequency drift compensation in BAW-based time reference application

In order to take up the challenge of BAW-based time reference, this paper presents new BAW/Integrated Circuits (IC) co-integration considerations. For the demonstration, a SiP approach is proposed where the Solidly Mounted Resonator (SMR) has been directly flip-chipped on the top of the IC. This 2.5 GHz oscillator reaches a -93 dBc/Hz phase noise at a 2 kHz carrier offset for a 7.3 mW power consumption. A 5 bit switched capacitor bank permits to correct process deviations with a 12.5 kHz accuracy while a varactor capacitance allows compensating a SMR with a -4.2 ppm/°C Temperature Coefficient of Frequency (TCF) in a [-40°C,85°C] temperature range.