Gate-level synthesis for low-power using new transformations

A new logic optimization method of multi-level combinational CMOS circuits is presented, which minimizes both power as well as power dissipation per unit area. The method described here uses Boolean transformations which exploit implications at the gate-level, based on both controllability and observability relationships. New transformations which form the basis of our synthesis method are presented. The emphasis is on power consumption rather than on area. Experimental results demonstrate that circuits synthesized by our method consume less power with a comparable area than those synthesized by state-of-the-art tools.