Design and FPGA implementation of radix-10 algorithm for square root with limited precision primitives

We present a radix-10 fixed-point digit-recurrence algorithm for square root using limited-precision multipliers, adders, and table-lookups. The algorithm, except in the initialization steps, uses the digit-recurrence algorithm for division with limited-precision primitives. We discuss the proposed square root algorithm, a design, and its FPGA implementation on a Xilinx Virtex-5 FPGA. We present the cost and delay characteristics for precisions of 7 (single-precision), 8, 14 (double-precision), 16, 24, and 32 decimal digits. The costs range from 720 to 2263 LUTs with maximum clock frequencies around 53MHz, and latencies ranging from 133 to 597 ns (with unoptimized routing delays). The proposed scheme uses short (2-3 digit-wide) operators which leads to compact modules, and may have an advantage at the layout level as well as in power optimization. The proposed approach is general and can be adapted to other higher radix square root implementations. Moreover, a combined scheme for division and square root can be efficiently implemented.