A universal structure for SRAM cell characterization

A universal test structure (UTS) for SRAM cell characterization is proposed and implemented in 65nm - 28nm technologies. The structure allows, for the first time, measurement of nearly all transistor and cell characteristics of an SRAM cell on silicon. It hence enables direct correlation among various measured transistor and cell characteristics, collection of intra-bit transistor mismatch data, and assessment of wafer level Vmin sensitivity on transistor characteristics. Measured data are presented.