Test Pattern Dependent FPGA Based System Architecture for JTAG Tests

The paper describes a new approach to speed-up and improve boundary scan based testing, by assigning functionality to a layer concept implemented in programmable logic. The motivation is driven by the constantly increasing gap between available and testable functionality of printed circuit boards. The motivation, architecture and build process of the proposed test and validation system is presented. Furthermore one selected example and first results are given to indicate the advantage of the proposed concept.