Estimation of Power Switching Current by Chip-Package-PCB Cosimulation

This paper presents a methodology to estimate power switching current on printed circuit boards (PCBs) through chip-package-PCB cosimulation. A macromodel for a timing controller chip running pseudo H-pattern data was generated from transistor-level simulations. The macromodel consists of a passive impedance network and internal switching activity of the chip. Power delivery network models for package and PCB were produced as a RLCG netlist and S-parameter touch stone files, respectively, using commercial tools. It is found that comparison between the simulated and measured impedances of the chip and package shows excellent agreement up to 300 MHz. Also, the simulated and measured impedances of the PCB match well in terms of magnitude and resonance frequency up to 3 GHz. Moreover, the results of power switching current from cosimulation and measurement show good agreement within 5 dB difference at major harmonic frequencies of 20 MHz data and 80 MHz clock patterns up to 1 GHz.