Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

A new analog-to-digital converter (ADC) technology called Single-slope look ahead ramp (SSLAR) analog-to-digital converter (ADC) was proposed for column-parallel CMOS image sensors. Additionally, a corresponding programmable ramp generator for SSLAR ADC was also designed in such a way that it only allows flexible code hopping (between 0 and 127 least significant bit (LSB)), code fall back and look-ahead operations in column-parallel ramp ADC. This new ADC technology is able to provide conversion speed improvement depending on individual image information with less than 1.0% image quality degradation. Simulation demonstrated that the conversion speed of this new ADC technology is 4-5x higher than a traditional single-slope ADC with minimal circuitry for processing 8-bit standard gray images as well as 3-4x for standard CIF videos. For processing higher resolution images, the conversion speed may further increase. A prototype chip using the 8-bit SSLAR ADC architecture was realized in a 0.5 ¿m, 2P3M, CMOS process with a layout area of 8.2 mm
²
.